ECE Electronic Circuits I Dec 2009

ANNA UNIVERSITY – CHENNAI
B.E.\B.TECH.DEGREE-EXAMINATION-DECEMBER 2009
THIRD SEMESTER-ELECTRONICS &COMMUNICATIONS ENGG.
ELECTRONIC CIRCUITS-I

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PART A-(2*10=20)
1. Define stability factor.
2. Draw the fixed bias single stage transistor circuit.
3. Define CMRR.
4. Draw the small signal equivalent circuit of FET.
5. Two amplifiers having gain 20db and 40db are cascaded. Find the overall gain in db.
6. Define bandwidth.
7. What is theoretical maximum conversion efficiency of class A power amplifier.
8. What is distortion in power amplifiers.
9. Draw the full wave bridge rectifier circuit.
10. What are the advantages of SMPS over conventional regulators.

PART B-(5*16=80)

11. A) (i) For the transistor circuit in fig. find the Q-point. Vcc=15v, B=100, VBE=0.7V

(ii) Calculate the stability factor for a fixed bias circuit.
B) Discuss the various techniques of stabilization of Q-point in a transistor.

12. A) For the CC transistor amplifier circuit, find the expressions for input impedance and voltage gain. Assume suitable model for transistor. (Or)
B) (i) Discuss the working of a basic emitter coupled differential amplifier circuit (8)
(ii) Compare CB, CE and CC amplifiers. (8)

13. A) (i) Discuss the frequency response of multistage amplifiers. Calculate the overall upper and lower cutoff frequencies. (10)
(ii) Discuss the terms rise time and sag. (6) (Or)
B) Discuss the high frequency equivalent circuit of FET and hence derive gain bandwidth product for any one configuration.
14. A) (i) Derive the theoretical max conversion efficiency of class B power amplifier. (10)

(ii) Write short notes on power MOSFET amplifier. (6) (Or)
B) Describe the distortion in power amplifier and the methods to eliminate the same.

15. A) Explain the circuit of voltage regulator and also discuss the short circuit protection mechanism. (Or)
B) (i) Explain the power control method using SCR.
(ii) Design zener regulator for following specification Vin=8v to 12v; Vo=10v, RL=10kO. Assume that zener diode is ideal.

ECE EC1401 VLSI Desig Nov/Dec 2009

B.E/B.Tech Degree Examination,November/December 2009.
Seventh Semester
Electronics and Communication Engineering
EC 1401-VLSI DESIGN
(Common to B.E.(Part-Time) Sixth Semester Regulation 2005)
(Regulation 2004)

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Part A-(10*2=20 marks)
1.What are the different MOS layers?
2.What are the two types of layout design rules?
3.Define rise time and fall time.
4.What is a pull down device?
5.What are the difference between task and function?
6.What is the difference between === and == ?
7.What is CBIC ?
8.Draw an assert high switch condition if input = 0 and input =1.
9.What do you mean by DFT?
10.Draw the boundary scan input logic diagram.

Part B - (5*16=80 marks)

11.a) Discuss the steps involved in IC fabrication process.(16)
Or
b) Describe n-well process in detail.(16)

12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8)
ii)Explain channel length modulation and body effect.(8)
Or
b)i)Explain the different regions of operation in a MOS transistor.(10)
ii)Write a note on MOS models.(6)

13.a)Explain in detail any five operators used in HDL .(16)
Or
b)i)Write the verilog code for 4 bit ripple carry full adder.(10)
ii)Give the structural description for priority encoder using verilog.(6)

14.a)Explain in detail the sequence of steps to design an ASIC.(16)
Or
b)Describe in detail the chip with programmable logic structures.(16)

15.a)Explain in detail Scan Based Test Techniques.(16)
Or
b)Discuss the three main design strategies for testability.(16)